Video by pantechelearning via YouTube
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21 DAYS MASTERCLASS PLAN:

DAY 1 – Introduction to VLSI
DAY 2 – Introduction to FPGA
DAY 3 – Tool installation – intel quartus
DAY 4 – Introduction to MAX10 FLK FPGA Board
DAY 5 – Digital electronics — number system, Boolean algebra and Logic Gates, Karnaugh map (k-map).
DAY 6 – Combination switching circuits & logic gates.
DAY 7 – Flip-flop-functionalities &working.
DAY 8 – Registers-functionalities &working.
DAY 9 – Counters & digital memories
DAY 10 – Introduction to Verilog
DAY 11 – Three modelling styles in verilog–gate-level, dataflow, and behavioural.
DAY 12 – Combination circuits -Adder, encoders, decoders, mux with verilog.
DAY 13 – Sequential circuits – latchs with verilog
DAY 14 – Sequential circuits-flip-flops with verilog
DAY 15 – Shift registers with verilog
DAY 16 – Finite state machine-moore with verilog code.
DAY 17 – Finite state machine -mealy with verilog code.
DAY 18 – Implementation -MAX10 FPGA FLK Flash using JTAG.
DAY 19 – Controlling max10 FPGA Flash FLK board’s GPIOs
DAY 20 – Off-chip project: real time working with communication protocol-UART-RX.
DAY 21 – Off-chip project: real time working with communication protocol UART-Tx.

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